1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device, and especially to writing/erasing of memory cells in a flash memory.
2. Description of the Background Art
Of electrically rewritable nonvolatile semiconductor storage devices, flash memories capable of erasing the entire or a block of data by one operation are well known in the art. Such flash memories are disclosed for example in Japanese Patent Application Laid-open Nos. 2001-28428, 2001-85540, and 2001-85541.
FIGS. 6 to 13 are cross-sectional views illustrating a method of manufacturing a group of memory transistors (memory cells) in a conventional flash memory. Referring to the drawings, the manufacturing procedure will be described hereinbelow.
Initially, as shown in FIG. 6, a silicon oxide film 102 is grown to a thickness of about 100 angstroms by thermal oxidation on the surface of a P-type silicon substrate 101 having a (001) crystal orientation, and then a phosphorus-doped polycrystalline silicon layer 103 is deposited by low-pressure CVD to a thickness of about 2000 angstroms. Following this, a silicon oxide film 104 is deposited to a thickness of about 1500 angstroms by low-pressure CVD.
After a predetermined pattern of resist (not shown) is formed by photolithography techniques, as shown in FIG. 7, the silicon oxide film 104 is etched using the resist as a mask, thereby to obtain a patterned silicon oxide film 104a. Using the silicon oxide film 104a as a mask, the phosphorus-doped polycrystalline silicon layer 103 is patterned to form a plurality of floating gates 103a. 
Then, arsenic ions 111 are angularly implanted at an implant energy of 40 keV and a dose of 5xc3x971015 cm2 as shown in FIG. 8, and the annealing is carried out in a nitrogen atmosphere, whereby N+ diffusion regions 105 of memory transistors are formed. At this time, parts of the N+ diffusion regions 105 are formed under the floating gates 103a. 
As shown in FIG. 9, exposed portions of the silicon oxide film 102 and the silicon oxide film 104 are removed by etching in a HF solution, so that only the silicon oxide film 102 directly below the floating gates 103a remain as silicon oxide films 102r. Further, a three-layer insulating film 106, consisting of a silicon oxide film of about 50 angstroms thick, a silicon nitride film of about 100 angstroms thick, and a silicon oxide film of about 50 angstroms thick, is deposited over the whole surface by low-pressure CVD.
Following this, as shown in FIG. 10, a phosphorus-doped polycrystalline silicon layer 107 is deposited over the whole surface to a thickness of about 1000 angstroms by low-pressure CVD.
The phosphorus-doped polycrystalline silicon layer 107 is, as shown in FIG. 11, etched back so that only the portions thereof on the three-layer insulating film 106 where the floating gates 103a are not formed, remain as a plurality of access gates 107a. Thus the other parts of the N+ diffusion regions 105 are located under the access gates 107a. That is, the N+ diffusion regions 105 each are formed under one floating gate 103a and one access gate 107a to extend thereacross.
The surfaces of the access gates 107a are thermally oxidized to form a silicon oxide film 108 of about 300 angstroms thick, as shown in FIG. 12.
Then, as shown in FIG. 13, a phosphorus-doped polycrystalline silicon layer 119 of about 2000 angstroms thick and a silicon oxide film 120 of about 2200 angstroms thick are successively deposited by low-pressure CVD.
After a predetermined pattern of resist (not shown) is formed on the silicon oxide film 120 by photolithography techniques, the silicon oxide film 120 is etched using the resist as a mask and the resist is removed. Further, the phosphorus-doped polycrystalline silicon 119 is etched using the silicon oxide film 120 as a mask, whereby a control gate 109 is formed.
FIG. 14 is a plan view illustrating a plan configuration after the formation of the control gate 109. As shown, a plurality of lines of control gates 109 are formed, each extending from side to side. FIG. 13 is the equivalent of a cross section of FIG. 14 taken along the line Axe2x80x94A.
As illustrated in the cross-sectional view of FIG. 15 and the plan view of FIG. 16, the three-layer insulating film 106 formed on the floating gates 103a, and the floating gates 103a are removed by etching using the silicon oxide film 120 as a mask. Thereby the patterning of the floating gates 103a is completed and the silicon oxide film 120 is removed. FIG. 16 is the equivalent of a cross section of FIG. 15 taken along the line Bxe2x80x94B.
In this fashion, one memory transistor is formed of the control gate 109, a set of one floating gate 103a and one access gate 107a that are adjacent to each other with the three-layer insulating film 106 sandwiched in between, and a pair of N+ diffusion regions 105, parts of which are formed under the above set of one floating gate 103a and one access gate 107a. By forming a plurality of such memory transistors adjacent to one another, a group of memory transistors can be obtained.
Referring to FIG. 13, for example, one memory transistor MT(n) is formed of the control gate 109, a floating gate 103a(n), an access gate 107a(n), and N+ diffusion regions 105(n) and 105(n+1).
The plurality of N+ diffusion regions 105 are configured such that their respective potentials can be set individually for reasons of necessity to perform a write operation for each memory transistor. The plurality of access gates 107a are configured such that at least adjacent access gates 107a can be set at different potentials for reasons of necessity to ensure normal write operations.
For instance, the plurality of access gates 107a are configured such that the potentials of a group of access gates {107a(nxe2x88x923), 107a(nxe2x88x921), 107a(n+1), and 107a(n+3)} and a group of access gates {107a(nxe2x88x922), 107a(n), and 107a(n+2)} can be set on an individual basis.
In the flash memory with such a memory transistor structure, the contents of information to be stored in each memory transistor is determined according to whether the memory transistor has a high threshold voltage Vthp due to electron injection in its floating gate 103a or has a low threshold voltage Vthe due to electron emission from its floating gate 103a. 
A memory transistor that has a high threshold voltage Vthp due to electron injection in its floating gate 103a is regarded as being in a written state. Since electrons stored in the floating gate 103a will not be destroyed semi-permanently unless they are forcedly emitted for example by an erase operation, information stored therein is also semi-permanent. A memory transistor that has a low threshold voltage Vthe due to electron emission from its floating gate 103a, on the other hand, is regarded as being in an erased state.
By detecting the state of each memory transistor, either xe2x80x9cwrittenxe2x80x9d or xe2x80x9ceasedxe2x80x9d, information stored in the memory transistor (memory cell) can be read.
FIG. 17 is a cross-sectional view for explaining a write operation on memory cells in a conventional flash memory. Referring to the drawing, the write operation on the memory cells will be described hereinbelow.
For convenience of explanation, the plurality of floating gates 103a are designated by 103a(nxe2x88x923) to 103a(n+3), the plurality of N+ diffusion regions 105 by 105(nxe2x88x923) to 105(n+3), and the plurality of access gates 107a by 107a(nxe2x88x924) to 107a(n+3) (the same applies to FIG. 18).
The n-th memory transitory MT(n) is formed of the control gate 109, the floating gate 103a(n), the access gate 107a(n), and the N+ diffusion regions 105(n) and 105(n+1).
In this configuration, a write operation on the memory transistor MT(n) is performed by applying a high voltage Vp2 (approximately 12 V) to the control gate 109, grounding the P-type silicon substrate 101, and setting the access gate 107a(n) at 2V and the access gates 107a(nxe2x88x921) and 107a(n+1) at 0V.
In writing for setting the memory transistor MT(n) to a high threshold voltage Vthp, for example, the N+ diffusion regions 105(n) and 105(n+1) are set at 5V and 0V respectively.
This produces hot electrons in a channel region in the surface of the P-type silicon substrate 101 between the N+ diffusion regions 105(n+1) and 105(n) and thereby causes electron injection in the floating gate 103a(n). The threshold voltage of the memory transistor MT(n) is thus increased to Vthp.
FIG. 18 is a cross-sectional view for explaining an erase operation on memory cells in a conventional flash memory. Referring to the drawing, the erase operation on the memory cells will be described hereinbelow. A plurality of memory transistors (e.g., all the memory transistors) are generally erased by one erase operation; in the present example, erasing of the memory transistors MT(nxe2x88x923) to MT(n+3) is performed by one operation.
The erase operation is performed by applying a high negative voltage Ve2 (approximately xe2x88x9216 V) to the control gate 109 and grounding the P-type silicon substrate 101, the plurality of N+ diffusion regions 105 (105(nxe2x88x923) to 105(n+3)), and the plurality of access gates 107a (107a(nxe2x88x924) to 107a(n+3)).
Accordingly, electrons are emitted by a tunneling effect from the plurality of floating gates 103a (103a(nxe2x88x923) to 103a(n+3)) to the P-type silicon substrate 101. This collectively reduces the threshold voltages of all the memory transistors MT(nxe2x88x923) to MT(n+3) to Vthe.
Next, a read operation for reading out information stored in the memory transistor MT(n) will be set forth. This read operation is performed, for example, by applying 3.3 V to the control gate 109 and 1.0 V to the N+ diffusion region 105(n) and setting the N+ diffusion region 105(n+1) and the P-type silicon substrate 101 at 0V, the access gate 107a(n) at 3.3 V, and the access gates 107a(nxe2x88x921) and 107a(n+1) at 0V.
Where Vthp greater than 3.3 (V) greater than Vthe, the memory transistor MT(n), when in the written state, is off and no current flows between source and drain (between the N+ diffusion regions 105(n) and 105(n+1)), while when in the erased state, the memory transistor MT(n) is on and current flows between source and drain. By detecting the presence or absence of the current flow between source and drain, information stored in the memory transistor MT(n) can be read.
The conventional flash memory performs read/erase/write operations as above described. It, however, offers the following problems.
(1) To set the memory transistor MT(n) to a high threshold voltage Vthp in writing, the N+ diffusion region 105(n) is set at 5 V, the N+ diffusion region 105(n+1) at 0 V, the access gate 107a(n) at 2 V, and the access gates 107a(nxe2x88x921) and 107a(n+1) at 0 V.
That is, the write operation on a desired memory transistor MT(n) imposes restrictions on the potential of the N+ diffusion region 105 of another memory transistor MT(n+1) adjacent to one side (n+1) of the memory transistor MT(n) and the potentials of the access gates 107a of two memory transistors MT(n+1) and MT(nxe2x88x921) adjacent to both sides (n+1) and (nxe2x88x921) of the memory transistor MT(n).
It is thus impossible to perform, simultaneously with the write operation for setting the memory transistor MT(n) to a high threshold voltage Vthp, write operations for setting the memory transistors MT(nxe2x88x921) and MT(n+1) adjacent to the memory transistors MT(n) to a high threshold voltage Vthp.
The write operations on the memory transistors MT(n+1) and MT(nxe2x88x921), therefore, have to be performed after the completion of the write operation on the memory transistor MT(n). This requires at least two write operations as above described to complete writing of all the memory transistors, thereby lengthening an entire write time for the flash memory.
(2) The erase operation is performed by electron emission from the floating gate 103a to the P-type silicon substrate 101 by the tunneling effect. This, however, requires the application of a relatively high negative voltage Ve2 (e.g., approximately xe2x88x9216 V) to the control gate 109 to achieve a desired erasing speed.
It is an object of the present invention to provide a nonvolatile semiconductor storage device capable of achieving a shortened write time and a reduced absolute value of the operating voltage at the time of erasing.
A first aspect of the present invention is directed to a method of writing of a nonvolatile semiconductor storage device. The nonvolatile semiconductor storage device includes a semiconductor substrate, a plurality of floating gates, a plurality of access gates, a plurality of diffusion regions, and a control gate. At least the surface of the semiconductor substrate is of a first conductivity type. The plurality of floating gates and the plurality of access gates are formed on an insulating film provided on the surface of the semiconductor substrate. The plurality of floating gates and the plurality of access gates are alternately formed adjacent to one another, with an insulating film sandwiched between each of the gates. The plurality of diffusion regions of a second conductivity type are selectively formed in the surface of the semiconductor substrate. The plurality of diffusion regions each are formed under a corresponding one of the plurality of floating gates and a corresponding one of the plurality of access gates to extend thereacross. The control gate is formed on an insulating film provided on the plurality of floating gates and the plurality of access gates. One memory transistor consists essentially of the control gate, a pair of adjacent ones of the plurality of diffusion regions, one of the plurality of floating gates which is formed on one of the pair of diffusion regions, and one of the plurality of access gates which is formed on the other one of the pair of diffusion regions. The method includes the following steps (a) to (d). The step (a) is to set the semiconductor substrate at a substrate potential. The step (b) is to set the control gate at a first potential higher than the substrate potential. The step (c) is to set the plurality of access gates at a second potential at which the surface of the semiconductor substrate under the plurality of access gates is not reversed to the second conductivity type. The step (d) is to set the one of the pair of diffusion regions in the one memory transistor at a third potential in a first write mode and to set the one of the pair of diffusion regions at a fourth potential that is shifted from the third potential toward the first potential in a second write mode. The first and third potentials include a potential at which electrons move from the one of the pair of diffusion regions to the one of the plurality of floating gates by a tunneling effect, and the first and fourth potentials include a potential at which substantially no electrons move from the one of the pair of diffusion regions to the one of the plurality of floating gates by the tunneling effect.
In the step (d), the threshold voltage of a memory transistor, when written in the first write mode, is increased by tunnel injection of electrons into the floating gate, whereas the threshold voltage of a memory transistor, when written in the second write mode, is maintained as-is without substantial tunnel injection of electrons into the floating gate. This achieves the write operation in which the contents of writing can be changed depending on the write mode, either xe2x80x9cthe first write modexe2x80x9d or xe2x80x9cthe second write modexe2x80x9d.
Further, the step (c) is performed in order not to reverse the surface of the semiconductor device under the plurality of access gates to the second conductivity type. Since the plurality of diffusion regions are electrically isolated from one another, the write operation is not interfered even if the potentials of the plurality of diffusion regions are simultaneously set.
This allows writing of the plurality of memory transistors to be performed by one operation, thereby achieving a shortened write time.
A second aspect of the present invention is directed to a method of erasing of a nonvolatile semiconductor storage device. The nonvolatile semiconductor storage device includes a semiconductor substrate, a plurality of floating gates, a plurality of access gates, a plurality of diffusion regions, and a control gate. At least the surface of the semiconductor substrate is of a first conductivity type. The plurality of floating gates and the plurality of access gates are formed on an insulating film provided on the surface of the semiconductor substrate. The plurality of floating gates and the plurality of access gates are alternately formed adjacent to one another, with an insulating film sandwiched between each of the gates. The plurality of diffusion regions of a second conductivity type are selectively formed in the surface of the semiconductor substrate. The plurality of diffusion regions each are formed under a corresponding one of the plurality of floating gates and a corresponding one of the plurality of access gates to extend thereacross. The control gate is formed on an insulating film provided on the plurality of floating gates and the plurality of access gates. One memory transistor consists essentially of the control gate, a pair of adjacent ones of the plurality of diffusion regions, one of the plurality of floating gates which is formed on one of the pair of diffusion regions, and one of the plurality of access gates which is formed on the other one of the pair of diffusion regions. The method includes the following steps (a) to (d). The step (a) is to set the semiconductor substrate at a substrate potential. The step (b) is to set the control gate at a first potential lower than the substrate potential. The step (c) is to set the plurality of access gates at a second potential. The step (d) is to set all of the plurality of diffusion regions at a third potential. The first and third potentials include a potential at which electrons stored in the plurality of floating gates are emitted to the semiconductor substrate by a tunneling effect, and the second potential includes a potential that is shifted from the substrate potential toward the first potential.
The second potential which is the potential of the plurality of access gates is equivalent to a potential that is shifted from the substrate potential toward the first potential which is the control gate potential.
In this case, the two capacitances (adjacent access gate capacitances) formed between the floating gate and two adjacent access gates improves the ratio of the floating gate potential to the control gate potential. Consequently, the absolute value of the operating voltage at the time of erasing, which is determined by the control gate potential, is reduced by the amount of increase in the above ratio.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.